The present invention relates to phase locked loop circuits, and more particularly, to phase locked loop circuits that are used to control the data rates of signal transmitters.
Phase locked loop circuits are well known to those of skill in the art. Phase locked loops circuits are used in signal processing applications.
A typical phase locked loop includes a phase detector, a charge pump, a loop filter, and a voltage controlled oscillator. The phase detector produces an output signal that is proportional to the phase difference between an input signal and a clock signal. The output signal of the phase detector is also proportional to the frequency difference between the input signal and the clock signal.
The charge pump and the loop filter together act as a low pass filter. The low pass filter filters the output signal of the phase detector to produce a DC voltage. The DC voltage is proportional to the phase difference between the input signals of the phase detector.
The oscillator outputs the clock signal. The phase of the clock signal is dependent on the output of the loop filter. The clock signal is provided to one of the input terminals of the phase detector. The phase detector compares the clock signal from the oscillator to the input signal of the phase locked loop. An amplifier may be used to step up the voltage at the output of the phase detector.
In some types of communication systems, data is transmitted with a predetermined structure called a frame. The frame contains a header section and a payload section. The actual data resides in the payload section. Different data transfer protocols may require a different amount of data bits in the frame. Data transmission from one such protocol to another can only be performed if the frame is adjusted.
Phase locked loop circuits may be used to generate a clock signal that is used by a transmitter to transmit data. It would therefore be desirable to provide a phase locked loop that can adjust the frame for particular data transmission protocols.